This invention is generally related to a method for interconnecting integrated circuits with high volumetric efficiency and, more particularly, to a method of applying edge metallization on a substrate for use in a three-dimensional module.
A method of selectively interconnecting the edge contact areas of a plurality of tightly stacked substrates having integrated circuit patterns thereon is described in Eichelberger et al., U.S. Pat. No. 5,019,946, issued May 28, 1991, wherein I/O (input/output) metal fingers (metallization exposed to areas outside the integrated circuit) were extended over the edges of the substrate. Extending titanium/aluminum I/O metal fingers over the substrate edges during I/O metal patterning prior to circuit fabrication is difficult because these are sputter-deposited films and thickness conformality over an edge is about forty percent. Even if it were possible to reliably use titanium and aluminum, it would be difficult to protect the metal during subsequent processing because the I/O metal on the substrate edge, unlike the I/O metal on the top, is exposed. As a result, aluminum and titanium would be exposed to all wet chemical treatments normally encountered during circuit fabrication. These metals are not compatible with many chemicals and would be etched away.
A method for extending an electrical conductor over an edge of an HDI substrate is described in Gorczyca et al., U.S. Pat. No. 5,285,571, issued Feb. 15, 1994. In Gorczyca et al., "an edge metal last" process is used in which the I/O metal fingers of a two dimensional (2D) high density interconnect (HDI) module are extended over the edge of a substrate at the end of circuit fabrication. The module includes a first dielectric layer covering one or more electrical conductors on a substrate. The first dielectric layer is ablated to expose a portion of at least one electrical conductor and a second dielectric layer is then applied over the first dielectric layer and the exposed portion of the electrical conductor except for an extremity of the conductor. A second electrical conductor is subsequently applied and patterned to cover a portion of the second dielectric layer, the extremity of the conductor, and at least a portion of one edge of the substrate.
The fabrication sequence in Gorczyca et al. requires many processing steps. Furthermore, patterning of edge fingers (whether prior to 2D module fabrication or after 2D module fabrication) requires a conformal electrophoretic resist coating which is substantially free of defects. Laser patterning of such edges requires a precision placement of 45 degree angled mirrors on the laser stage because mirror misplacement can create laser focus problems. Moreover, the patterned edge fingers are difficult to protect during fixturing of the stack.
When the edge fingers are applied after 2D module fabrication, an air gap is formed between adjacent modules and creates a non-planar stack edge with alignment problems that can hinder the fabrication of stacks with more than four layers.